1. Field of the Invention
The invention pertains to the field of semiconductor manufacturing processes. More particularly, the invention pertains to a method of manufacturing a semiconductor device with structural elements having varying thicknesses in a common layer.
2. Description of the Related Technology
Complementary Metal-Oxide Semiconductor (CMOS) integrated circuits combine both n-type (nMOS) and p-type (pMOS) field effect transistors (FET). These two types of transistors are also commonly referred to as n-channel, or nMOS, and p-channel, or pMOS, devices, respectively. Methods of fabricating CMOS integrated circuits are well known in the technology. Areas are selected on a semiconductor substrate, such as silicon, where transistors will be formed during subsequent processing. These so-called “active areas” are insulated from each other by forming insulation structures between the areas. Examples of such insulation structures are locally oxidized silicon (LOCOS) or shallow trenches filled with dielectrics (STI). Active areas where nMOS or pMOS devices are to be formed can be labeled respectively as nMOS or pMOS active areas.
A gate dielectric is formed on the surface of the semiconductor substrate, where the gate dielectric is typically formed by oxidizing the silicon surface or by forming a stack comprising high-k dielectrics on the substrate. A gate electrode is formed on top of this gate dielectric. Typically the gate electrode is formed by deposition of a semiconducting material such as polysilicon (pSi) or polysilicongermanium (pSiGe) or alloys thereof. This layered gate dielectric and electrode material is then patterned to yield the gate stack of the individual transistors.
The semiconductive gate electrode material is rendered conductive by doping it with dopants normally provided by an ion implantation source. Although the gate electrode material is common to both nMOS and pMOS devices, the doping of the gate electrode of both devices is performed separately by selectively masking regions comprising only one of both device types. During the doping of the gate electrode of the nMOS transistor, the source/drain junctions of the nMOS may also be formed, and, mutatis mutandis, during the doping of the pMOS transistor, the corresponding source/drain junctions may be formed in the non-masked active areas. The source/drain junctions serve as electrical contacts to the oppositely doped channel region, formed underneath the gate stack. Additional implantations can be performed over the course of processing, e.g. to form doped regions in the substrate such as a well or sink, or other implantations known to a person skilled in the art to obtain the desired electrical and functional behavior of the device to be processed can be performed.
Doping of the gate electrode generally has to meet several requirements. The ion implant dose (ions/cm2), used to simultaneously dope the gate electrode and the junction regions, must, for example, be high enough to obtain a sufficiently low resistivity in both the gate electrode and the source/drain junctions. The doping should ideally be uniform over the gate electrode, or at least to the interface with the underlying gate electrode. In the event the doping concentration (ions/cm3) at the gate dielectric/gate electrode interface is too low, this part of the gate electrode can be depleted if the field effect transistor is biased into inversion. Such unwanted depletion will have a negative impact on the electrical performance of the transistor: the depletion layer forms an additional capacitance in series with the gate capacitance and it diminishes the control of the gate voltage over the channel and bulk region leading to more severe short channel effects.
In the event a high implant energy is used to implant the ions into the gate electrode, then a uniformly doped gate electrode layer could be obtained. This implant energy however has to be within certain limits because the doping of the gate electrode must be confined to the gate electrode itself. If the gate dopants were to reach the oppositely doped channel region, the channel can be counterdoped, or at least the effective channel doping is reduced, leading to a change in the threshold voltage and the “short channel”-characteristics of the device. A high implant energy would also result in deep junctions whereas in submicron CMOS-based technologies shallow junctions are preferred because of the decreased short channel effects and junction capacitance. Alternately, if a low implant energy is used followed by thermal processing procedures, the above problems can be avoided, but during these, or other subsequent, thermal processing procedures, the gate dopants might diffuse from the gate electrode through the gate dielectric into the channel region and compensate the channel doping.
Penetration of the channel region during implantation of such heavy ions is unlikely to happen even at elevated implant energies due to the use of ions, such as P, As or Sb, to dope the gate electrode of an nMOS device. As the diffusion speed of these impurities is low, at least in the gate dielectric, the channel region will essentially not be penetrated by these heavy ions during thermal processing procedures following the implantation process. Alternately, the lighter ions, such as B, used to dope the gate electrode of a pMOS device are more likely to penetrate the channel through the thin gate dielectrics used in submicron MOS technologies. If the annealing conditions are optimized for pMOS transistors to avoid extensive boron penetration in the channel region, high gate depletion in an NMOS device might occur as the thermal energy or budget of the CMOS process is not sufficient to activate the n-type dopants or have them diffuse all over the gate electrode. The integration of both devices therefore requires careful optimization of implantation conditions and final annealing procedures.
Japanese patent application JP2000058668, which is hereby incorporated by reference, proposes a CMOS architecture where the polysilicon gate electrode has two thicknesses. The thinner nMOS gate electrode requires less diffusion of the n-type dopants, and hence less thermal energy is required to obtain a uniform doping of this gate electrode. The thicker pMOS gate electrode offers enough stopping capability to the implanted ions to prevent penetration of the channel. The thicker pMOS gate electrode enables an increase of the temperature of final RTA and thus improves the dopant activation without the risk of boron penetration. For a given thermal budget, the p-type impurities must diffuse a larger distance before they reach the gate electrode/gate dielectric interface or even the channel region. This so-called “dual gate” CMOS process facilitates the optimization of the process of the gate electrodes with respect to reduction of gate depletion in nMOS and boron penetration in the channel for the pMOS devices. The application describes several embodiments of methods of decreasing the thickness of the gate electrode for the nMOS devices or increasing the thickness of this gate electrode layer for the pMOS devices. These methods can be generalized as follows:                1. Mask the as-deposited polysilicon layer outside the regions of the nMOS devices, remove the polysilicon layer in these unmasked regions using a timed etching, e.g. a dry etching technique such as Reactive Ion Etching (RIE) during a predetermined period of time;        2. Deposit a multilayer structure of polysilicon/silicon oxide/polysilicon as gate electrode on the gate dielectric and remove the top polysilicon layer of this multilayer only in the regions where the nMOS devices will be formed;        3. Mask the as-deposited polysilicon gate electrode layer outside the region of the pMOS devices by a thin oxide layer and grow an additional silicon layer on the top of the non-oxidized regions of the as-deposited polysilicon layer;        4. Mask the as-deposited polysilicon gate electrode layer in the area of the pMOS devices by a thin nitride layer, oxide the non-masked polysilicon layer and remove the oxidized polysilicon layer by a wet etch process.        
The proposed method has several disadvantages with respect to process complexity and manufacturing capability. Additional topography is created between the nMOS and pMOS devices as the variation in thickness of the as-deposited polysilicon electrode is obtained prior to the patterning of this polysilicon layer. This difference in height influences the process latitude and control of the patterning process. During the process of etching the polysilicon layer, the gate stack of the nMOS device might be overetched resulting in attacking the underlying active area. This problem of “pitting” might be of more concern in a case where the electrode etching has to stop on thin gate dielectrics. The proposed sequences are therefore not suitable for use in scaled down CMOS processes.
If a dry etch technique is used to thin the as-deposited polysilicon layer in the nMOS regions, the underlying gate oxide is exposed to this etching plasma and plasma damage of the gate dielectric might occur. Timed etch processes typically result in high dispersion of the final thickness as no control over the etching parameters, such as etch speed, is performed. Thickening the as-deposited polysilicon layer in the region of the pMOS devices certainly adds to process complexity as masking steps have to be used as well as processes capable of selective growth. Selective growth or selective etching requires the presence of a masking or stopping layer. If this masking or stopping layer is not removed it will influence the electrical performance of the gate electrode and hence of the corresponding device.
Therefore, improved production and manufacturing methods of forming structural elements of various thicknesses within a common layer of a semiconductor device would be beneficial in the technology.